module IDEX(
    input clk, rst, 

    input RegW, 
    output reg EX_RegW, 

    input [1:0] Mem2R, 
    output reg [1:0] EX_Mem2R, 

    input Branch, 
    output reg EX_Branch, 

    input MemR, 
    output reg EX_MemR,

    input MemW, 
    output reg EX_MemW, 

    input [1:0] RegDst, 
    output reg [1:0] EX_RegDst, 

    input [4:0] ALUOp, 
    output reg [4:0] EX_ALUOp, 

    input Alusrc, 
    output reg EX_Alusrc, 

    input Alusrc1, 
    output reg EX_Alusrc1,

    input [31:0] RD1, 
    output reg [31:0] EX_RD1, 

    input [31:0] RD2, 
    output reg [31:0] EX_RD2, 

    input [31:0] Imm32, 
    output reg [31:0] EX_Imm32, 

    input [4:0] rt, 
    output reg [4:0] EX_rt, 

    input [4:0] rd, 
    output reg [4:0] EX_rd, 

    input [4:0] rs, 
    output reg [4:0] EX_rs, 

    input [31:0] ID_PC, 
    output reg [31:0] EX_PC, 

    input [25:0] IMM, 
    output reg [25:0] EX_IMM, 

    input IDEX_Flush
);

    always @(posedge clk, posedge rst)
    begin
        if (rst | IDEX_Flush)
        begin
            EX_ALUOp = 0;
            EX_Alusrc = 0;
            EX_Alusrc1 = 0;
            EX_Branch = 0;
            EX_Imm32 = 0;
            EX_Mem2R = 0;
            EX_MemR = 0;
            EX_MemW = 0;
            EX_rd = 0;
            EX_RD1 = 0;
            EX_RD2 = 0;
            EX_RegDst = 0;
            EX_RegW = 0;
            EX_rt = 0;
            EX_rs = 0;
            EX_PC = 0;
            EX_IMM = 0;
        end

        else
        begin
            EX_ALUOp = ALUOp;
            EX_Alusrc = Alusrc;
            EX_Alusrc1 = Alusrc1;
            EX_Branch = Branch;
            EX_Imm32 = Imm32;
            EX_Mem2R = Mem2R;
            EX_MemR = MemR;
            EX_MemW = MemW;
            EX_rd = rd;
            EX_RD1 = RD1;
            EX_RD2 = RD2;
            EX_RegDst = RegDst;
            EX_RegW = RegW;
            EX_rt = rt;
            EX_rs = rs;
            EX_PC = ID_PC;
            EX_IMM = IMM;
        end
    end

endmodule